Critical Technology

Advanced Semiconductor Fabrication

The capacity to fabricate semiconductors at or near the leading edge: the process technology, yield mastery and production know-how of advanced nodes. One of the capabilities of Semiconductors & Advanced Computing.

International families: 140k2015 to 2024
Leading country: Japan1.9× the next
All families: 273khome filings included
Over five years: Rising2020 to 2024 against the five before

Year by year

Patent families by country of origin and the year of the earliest filing, 2000 to 2025; 2025 is a part year, still filling in. International families are those for which protection was sought beyond one country.

Volume

International patent families in the capability, by the year of the earliest filing.

Source: Global Institute for National Capability (GINC), 2026. Underlying patents from 107 patent offices, IFI CLAIMS and Google

Share by country

Each country's share of the year's international families, in per cent: the capability's five largest countries of origin, 2015 to 2024, and the rest of the world.

Source: Global Institute for National Capability (GINC), 2026. Underlying patents from 107 patent offices, IFI CLAIMS and Google

Country leaderboard

International patent families, 2015 to 2024, by country of origin. Growth compares the latest five full years with the five before.

Ten largest

Japan

United States

South Korea

Taiwan

China

Germany

France

Netherlands

Singapore

Austria

44,951

23,299

22,064

19,873

15,776

3,694

2,247

2,056

1,109

787


1	Japan	44,951	32.1%	0.9×	66,090
2	United States	23,299	16.6%	1.0×	37,963
3	South Korea	22,064	15.7%	1.4×	36,228
4	Taiwan	19,873	14.2%	1.3×	27,816
5	China	15,776	11.3%	1.5×	86,425
6	Germany	3,694	2.6%	0.8×	4,335
7	France	2,247	1.6%	0.8×	2,525
8	Netherlands	2,056	1.5%	1.4×	2,198
9	Singapore	1,109	0.8%	2.2×	1,676
10	Austria	787	0.6%	1.0×	848
11	United Kingdom	625	0.4%	0.9×	764
12	Switzerland	608	0.4%	2.3×	668
13	Belgium	602	0.4%	0.9×	616
14	Italy	374	0.3%	0.9×	449
15	Israel	343	0.2%	1.5×	428
16	Canada	290	0.2%	1.7×	359
17	Cayman Islands	286	0.2%	0.1×	1,501
18	Finland	198	0.1%	1.1×	211
19	Sweden	140	0.1%	0.7×	145
20	Australia	110	0.1%	1.0×	119
21	Ireland	85	0.1%	0.8×	147
22	Hong Kong	67	0.0%	1.0×	109
23	Malaysia	57	0.0%	0.4×	94
24	Saudi Arabia	49	0.0%	0.2×	63
25	Luxembourg	42	0.0%	0.1×	43
26	Spain	38	0.0%	1.2×	44
27	Poland	36	0.0%	1.8×	117
28	Denmark	33	0.0%	0.7×	35
29	India	31	0.0%	0.7×	62
30	Norway	24	0.0%	0.4×	24
31	Türkiye	20	0.0%	2.3×	65
32	Russia	17	0.0%	0.4×	534
33	Portugal	11	0.0%	1.8×	12
34	Brazil	10	0.0%	1.0×	28
35	Czechia	8	0.0%	0.6×	16
36	Hungary	6	0.0%	5.0×	10
37	South Africa	5	0.0%	0.7×	5
38	Mexico	4	0.0%	3.0×	27
39	New Zealand	3	0.0%	0.0×	6
40	Liechtenstein	3	0.0%	–	3

Applicants

The largest applicants by international patent families, 2015 to 2024: across the world, then within each of the five countries with the most families in Advanced Semiconductor Fabrication. Names are as held in the source and are not consolidated across subsidiaries.

Global

140,156 international families

SAMSUNG ELECTRONICS CO LTD · South Korea

TAIWAN SEMICONDUCTOR MFG CO LTD · Taiwan

TOKYO ELECTRON LTD · Japan

TAIWAN SEMICONDUCTOR MFG · Taiwan

APPLIED MATERIALS INC · United States

INTEL CORP · United States

11,759

10,855

5,910

4,129

3,753

3,231

Japan

44,951 international families

TOKYO ELECTRON LTD

KIOXIA CORP

DISCO CORP

DISCO ABRASIVE SYSTEMS LTD

TOSHIBA MEMORY CORP

TOSHIBA KK

5,881

2,468

1,994

1,950

1,923

1,816

United States

23,299 international families

APPLIED MATERIALS INC

INTEL CORP

MICRON TECHNOLOGY INC

LAM RES CORP

IBM

QUALCOMM INC

3,709

3,211

1,895

1,394

938

895

South Korea

22,064 international families

SAMSUNG ELECTRONICS CO LTD

SK HYNIX INC

SAMSUNG DISPLAY CO LTD

SEMES CO LTD

LG DISPLAY CO LTD

SAMSUNG ELECTRO MECH

11,726

2,289

1,447

728

378

375

Taiwan

19,873 international families

TAIWAN SEMICONDUCTOR MFG CO LTD

TAIWAN SEMICONDUCTOR MFG

UNITED MICROELECTRONICS CORP

NANYA TECHNOLOGY CORP

MACRONIX INT CO LTD

WINBOND ELECTRONICS CORP

10,814

4,117

1,601

1,240

407

389

China

15,776 international families

BOE TECHNOLOGY GROUP CO LTD

CHANGXIN MEMORY TECH INC

YANGTZE MEMORY TECH CO LTD

2.0% shared · 3,825 families in both

Japan

United States

China

South Korea

Germany

15,415

10,867

7,351

5,927

5,220

Crosswalk

How Advanced Semiconductor Fabrication is matched to the patent classifications. The entries below were chosen for it; each stands for itself and everything beneath it in the scheme, 1,005 Cooperative entries in all. A patent family counts when any of its codes, in either scheme and at any office, falls under one of them. Codes since retired are placed under the entries that replaced them.

Entry	Title in the scheme	Why it is chosen	CPC codes	IPC codes	Documents
H10P	Generic processes or apparatus for the manufacture or treatment of devices covered by class h10	Semiconductor manufacturing processes: deposition, etch, implant, lithography steps	1,281	212	3,968,499
H10D30/01	Manufacture or treatment	Manufacture of field-effect transistors	198	12	617,164
H10D30/62	Fin field-effect transistors [FinFET]	FinFET transistors	8	1	101,444
H10D30/501	FETs having stacked nanowire, nanosheet or nanoribbon channels	Nanosheet and gate-all-around transistors	8	none	34,448
H10D84/00	Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers	Integrated circuits on semiconductor wafers, e.g. CMOS	190	44	1,090,185
H10D88/00	Three-dimensional [3D] integrated devices	Three-dimensional integrated devices	3	1	43,501
H10B	Electronic memory devices	Memory devices: DRAM, flash, resistive and magnetic memory	236	101	1,102,158
H10W10/00	Isolation regions in semiconductor bodies between components of integrated devices	Isolation regions between components in chips	32	8	284,968
H10W20/00	Interconnections in chips, wafers or substrates	On-chip interconnections and through-silicon vias	196	21	1,410,788
H10P72/00	Handling or holding of wafers, substrates or devices during manufacture or treatment thereof	Left out
H10D84/90	Masterslice integrated circuits	Left out
H10B80/00	Assemblies of multiple devices comprising at least one memory device covered by this subclass	Left out

CPC and IPC codes are the codes in use on patent documents, at any office, that fall under the entry. Documents is the larger of the two schemes' counts of documents carrying one of them. An entry with no IPC codes can be told apart only in the Cooperative scheme.

The Cooperative codes in use that count towards Advanced Semiconductor Fabrication: 2,152 codes on 8,653,155 documents. The 150 most used are listed; the full list is in the cpc-to-capability.csv download.

Code	Title	Under entry	How placed	Documents
H10D84/038	Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe	H10D84/00	In the scheme	166,020
H10P95/00	Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass	H10P	In the scheme	105,948
H10P52/00	Grinding, lapping or polishing of wafers, substrates or parts of devices	H10P	In the scheme	81,349
H10W20/20	Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]	H10W20/00	In the scheme	76,271
H10P50/283	Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means	H10P	In the scheme	73,490
H10P50/242	Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials	H10P	In the scheme	68,659
H10P14/24	Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]	H10P	In the scheme	66,330
H10P74/203	Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects	H10P	In the scheme	63,221
H10W20/42	Vias, e.g. via plugs	H10W20/00	In the scheme	60,064
H10P54/00	Cutting or separating of wafers, substrates or parts of devices	H10P	In the scheme	58,106
H10W20/056	Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches	H10W20/00	In the scheme	56,980
H10P14/3411	Silicon, silicon germanium or germanium	H10P	In the scheme	56,252
H10D30/024	Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]	H10D30/01	In the scheme	55,400
H10P95/90	Thermal treatments, e.g. annealing or sintering	H10P	In the scheme	54,323
H10B43/27	EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels	H10B	In the scheme	53,729
H10W20/40	Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes	H10W20/00	In the scheme	51,733
H10D30/62	Fin field-effect transistors [FinFET]	H10D30/62	In the scheme	50,915
H10W10/17	Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations	H10W10/00	In the scheme	49,764
H10P76/2041	Photolithographic processes	H10P	In the scheme	48,394
H10P50/73	Etching of wafers, substrates or parts of devices using masks for insulating materials	H10P	In the scheme	46,361
H10P14/6336	Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]	H10P	In the scheme	44,784
H10W20/43	Layouts of interconnections	H10W20/00	In the scheme	44,053
H10P14/69215	Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2	H10P	In the scheme	43,137
H10W20/081	Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts	H10W20/00	In the scheme	42,939
H10W10/014	Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations	H10W10/00	In the scheme	41,055
H10P50/00	Etching of wafers, substrates or parts of devices	H10P	In the scheme	40,719
H10W10/181	Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers	H10W10/00	In the scheme	39,898
H10P14/6339	Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD	H10P	In the scheme	39,335
H10W20/069	Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs	H10W20/00	In the scheme	39,071
H10D84/0158	Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs	H10D84/00	In the scheme	37,927
H10W20/023	Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias	H10W20/00	In the scheme	36,559
H10B41/30	Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region	H10B	In the scheme	36,176
H10B69/00	Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices	H10B	In the scheme	36,050
H10P76/00	Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography	H10P	In the scheme	35,896
H10W20/435	Cross-sectional shapes or dispositions of interconnections	H10W20/00	In the scheme	35,526
H10B41/27	Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels	H10B	In the scheme	35,219
H10P14/3416	Nitrides	H10P	In the scheme	34,955
H10B43/35	EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND	H10B	In the scheme	34,569
H10P74/23	Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes	H10P	In the scheme	34,033
H10D84/83	Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]	H10D84/00	In the scheme	33,978
H10P14/2905	Silicon, silicon germanium or germanium	H10P	In the scheme	32,858
H10P76/4085	Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks	H10P	In the scheme	32,840
H10P14/69433	Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz	H10P	In the scheme	32,265
H10P30/204	Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors	H10P	In the scheme	31,913
H10D84/85	Complementary IGFETs, e.g. CMOS	H10D84/00	In the scheme	31,906
H10B41/35	Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND	H10B	In the scheme	31,535
H10D84/0167	Manufacturing their channels	H10D84/00	In the scheme	30,917
H10W20/425	Barrier, adhesion or liner layers	H10W20/00	In the scheme	30,736
H10W20/033	Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics	H10W20/00	In the scheme	29,798
H10D30/015	Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT	H10D30/01	In the scheme	29,548
H10P74/00	Testing or measuring during manufacture or treatment of wafers, substrates or devices	H10P	In the scheme	29,333
H10D84/834	Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs	H10D84/00	In the scheme	28,741
H10D88/00	Three-dimensional [3D] integrated devices	H10D88/00	In the scheme	28,567
H10P50/642	Chemical etching	H10P	In the scheme	28,202
H10P14/20	Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials	H10P	In the scheme	27,939
H10D30/0321	Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon	H10D30/01	In the scheme	27,841
H10D84/00	Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers	H10D84/00	In the scheme	27,436
H10B12/00	Dynamic random access memory [DRAM] devices	H10B	In the scheme	27,049
H10D84/0193	Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs	H10D84/00	In the scheme	26,906
H10D84/811	Combinations of field-effect devices and one or more diodes, capacitors or resistors	H10D84/00	In the scheme	26,401
H10D84/01	Manufacture or treatment	H10D84/00	In the scheme	26,372
H10B43/40	EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region	H10B	In the scheme	26,371
H10D84/017	Manufacturing their source or drain regions, e.g. silicided source or drain regions	H10D84/00	In the scheme	26,069
H10D84/853	Complementary IGFETs, e.g. CMOS comprising FinFETs	H10D84/00	In the scheme	26,005
H10D84/0149	Manufacturing their interconnections or electrodes, e.g. source or drain electrodes	H10D84/00	In the scheme	25,832
H10P14/6334	Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition	H10P	In the scheme	25,817
H10P52/403	Chemomechanical polishing [CMP] of conductive or resistive materials	H10P	In the scheme	25,786
H10B43/10	EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout	H10B	In the scheme	25,575
H10W20/0698	Local interconnections	H10W20/00	In the scheme	25,123
H10D30/031	Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]	H10D30/01	In the scheme	25,093
H10P50/71	Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials	H10P	In the scheme	24,561
H10W20/089	Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning	H10W20/00	In the scheme	24,492
H10P30/21	Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species	H10P	In the scheme	24,307
H10P52/402	Chemomechanical polishing [CMP] of semiconductor materials	H10P	In the scheme	23,211
H10P14/6922	Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC	H10P	In the scheme	23,146
H10D30/0297	Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes	H10D30/01	In the scheme	23,016
H10D30/501	FETs having stacked nanowire, nanosheet or nanoribbon channels	H10D30/501	In the scheme	23,010
H10D84/0151	Manufacturing their isolation regions	H10D84/00	In the scheme	22,790
H10D30/0227	Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET	H10D30/01	In the scheme	22,663
H10B43/50	EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions	H10B	In the scheme	22,641
H10P70/20	Cleaning during device manufacture	H10P	In the scheme	22,575
H10W20/076	Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches	H10W20/00	In the scheme	22,478
H10W20/01	Manufacture or treatment	H10W20/00	In the scheme	22,406
H10P50/287	Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means	H10P	In the scheme	22,072
H10P34/42	Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing	H10P	In the scheme	21,978
H10P14/3216	Nitrides	H10P	In the scheme	21,848
H10P76/204	Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks	H10P	In the scheme	21,845
H10W20/077	Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors	H10W20/00	In the scheme	21,744
H10P95/062	Planarisation of inorganic insulating materials involving a dielectric removal step	H10P	In the scheme	21,502
H10B12/482	Bit lines	H10B	In the scheme	21,469
H10D30/0212	Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation	H10D30/01	In the scheme	21,251
H10B43/30	EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region	H10B	In the scheme	21,208
H10P14/6342	Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating	H10P	In the scheme	21,199
H10P10/00	Bonding of wafers, substrates or parts of devices	H10P	In the scheme	20,990
H10P14/22	Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using physical deposition, e.g. vacuum deposition or sputtering	H10P	In the scheme	20,532
H10W20/031	Manufacture or treatment of conductive parts of the interconnections	H10W20/00	In the scheme	20,504
H10D30/021	Manufacture or treatment of FETs having insulated gates [IGFET]	H10D30/01	In the scheme	20,485
H01L23/5226	Retired code	H10W20/00	Retired, by concordance	20,438
H10W20/427	Power or ground buses	H10W20/00	In the scheme	20,377
H10P14/60	Formation of materials, e.g. in the shape of layers or pillars of insulating materials	H10P	In the scheme	20,345
H10W20/48	Insulating materials thereof	H10W20/00	In the scheme	20,241
H10B61/00	Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices	H10B	In the scheme	19,936
H10P70/15	Cleaning before device manufacture, i.e. Begin-Of-Line process by wet cleaning only	H10P	In the scheme	19,829
H10P14/6682	Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane	H10P	In the scheme	19,797
H10B12/033	Making the capacitor or connections thereto the capacitor extending over the transistor	H10B	In the scheme	19,791
H10P14/40	Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials	H10P	In the scheme	19,714
H10P30/20	Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping	H10P	In the scheme	19,212
H10P74/207	Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics	H10P	In the scheme	19,096
H10D84/013	Manufacturing their source or drain regions, e.g. silicided source or drain regions	H10D84/00	In the scheme	18,853
H10B12/30	DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells	H10B	In the scheme	18,826
H10P14/3434	Deposited materials, e.g. layers characterised by the chemical composition being oxide semiconductor materials	H10P	In the scheme	18,446
H10B63/80	Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays	H10B	In the scheme	18,410
H10W20/47	Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants	H10W20/00	In the scheme	18,398
H10B12/315	DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line	H10B	In the scheme	18,132
H10D30/0411	Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates	H10D30/01	In the scheme	18,132
H10D84/0188	Manufacturing their isolation regions	H10D84/00	In the scheme	18,004
H10D30/6211	Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates	H10D30/62	In the scheme	17,915
H10B41/10	Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout	H10B	In the scheme	17,910
H10B12/0335	Making a connection between the transistor and the capacitor, e.g. plug	H10B	In the scheme	17,865
H10B61/22	Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type	H10B	In the scheme	17,719
H10W20/074	Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers	H10W20/00	In the scheme	17,687
H10D84/0135	Manufacturing their gate conductors	H10D84/00	In the scheme	17,674
H10B10/12	Static random access memory [SRAM] devices comprising a MOSFET load element	H10B	In the scheme	17,577
H10P74/277	Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers	H10P	In the scheme	17,565
H10D84/0128	Manufacturing their channels	H10D84/00	In the scheme	17,559
H10D30/6219	Fin field-effect transistors [FinFET] characterised by the source or drain electrodes	H10D30/62	In the scheme	17,440
H10D30/019	Manufacture or treatment of FETs having stacked nanowire, nanosheet or nanoribbon channels	H10D30/01	In the scheme	17,387
H10D30/025	Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs	H10D30/01	In the scheme	17,378
H10D30/0314	Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate	H10D30/01	In the scheme	17,088
H01L29/66795	Retired code	H10D30/01	Retired, by concordance	17,054
H10B41/40	Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region	H10B	In the scheme	16,967
H10D84/0186	Manufacturing their interconnections or electrodes, e.g. source or drain electrodes	H10D84/00	In the scheme	16,873
H10P90/1914	Preparing SOI wafers using bonding	H10P	In the scheme	16,810
H10P50/267	Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas	H10P	In the scheme	16,779
H10P14/43	Chemical deposition, e.g. chemical vapour deposition [CVD]	H10P	In the scheme	16,671
H10P30/22	Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks	H10P	In the scheme	16,639
H10D30/014	Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors	H10D30/01	In the scheme	16,582
H10P14/2921	Materials being crystalline insulating materials	H10P	In the scheme	16,443
H10B12/05	Making the transistor	H10B	In the scheme	16,426
H01L29/66545	Retired code	H10D30/01	Retired, by concordance	16,377
H10B43/20	EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels	H10B	In the scheme	16,328
H10P32/171	Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material	H10P	In the scheme	16,178
H10P76/405	Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks	H10P	In the scheme	16,149
H10P90/1916	Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut	H10P	In the scheme	16,078
H10P50/695	Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask	H10P	In the scheme	15,956
H10B63/30	Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors	H10B	In the scheme	15,883
H10W20/496	Capacitor integral with wiring layers	H10W20/00	In the scheme	15,753
H10W10/01	Manufacture or treatment	H10W10/00	In the scheme	15,736
H10P90/1906	Preparing SOI wafers	H10P	In the scheme	15,683
H10P14/3238	Materials thereof being insulating materials	H10P	In the scheme	15,587

Match: Direct

The capability is itself a technology or a kind of physical system, and the classification names it. Older H01L entries are absent from the scheme, so documents carrying only H01L codes are not matched; wafer-handling apparatus and memory assemblies are carved out to sibling capabilities. The crosswalk is a first pass that nobody has reviewed.

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